Abstract
White beam synchrotron x-ray topography (WBSXRT) is a non-destructive technique, which is capable of analysing the strain and/or dislocation distribution in single crystal materials. This paper discusses the application of WBSXRT to the analysis of strain fields due to the microelectronic packaging of integrated circuits. A ball grid array package containing an Intel® Pentium® III microprocessor was employed to investigate the spatial extent of strain fields imposed on the underlying silicon substrate due to the reflow process for lead–tin solder bumps.
Large area and section back-reflection SXRT images were taken before and after the reflow process at 350°C in atmosphere. The effects of strain imposed by the overlying bump structures in these x-ray topographs have been observed principally via orientational contrast. This was also the situation after the reflow process due to severe stresses in the underlying silicon beneath the lead bumps. The estimated magnitudes of shear stress, |τxy|, imposed on the underlying silicon were calculated to be of the order of 100 MPa. A simulation of the orientational contrast at the edge of bump was performed based on the kinematical theory of x-ray diffraction (Rantamäki R et al 1999 J. Appl. Phys. 86 4298). The degree of lattice distortion is well fitted to the topographs of the post-reflow sample. The spatial strain in the underlying silicon was relieved dramatically after the lead bumps were removed from the wafer, which confirms that the solder bump formation is indeed a major source of strain in the underlying Si. Finite element modelling was performed in two-dimensional plane strain mode. The magnitudes and spatial distribution of the stresses after the reflow process are in good agreement with the SXRT results.
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