Correlating integrated circuit process-induced strain and defects against device yield and process control monitoring data

Abstract

Synchrotron X-ray section topographs and etch-pit micrographs of the wafers processed in a CMOS fab, are analyzed and correlated against the measured process-control monitoring data and the device yield obtained from the wafers. The etch-pit micrographs detail precipitates, dislocations, and stacking faults, whereas the X-ray topographs additionally show the strain gradient-caused by lattice bending and misfit. Specifically written image-processing software extracts features from the digitized topographs and micrographs after making computational adjustments. These extracted feature parameters are correlated against the electrically and optically obtained process-control monitoring data, collected from the wafer-processing results, and against the yield obtained from the wafer-probing stage. Several image features extracted from the synchrotron X-ray topographs exhibit a strong correlation to certain measured process parameters, e.g., PMOS transistor threshold voltage, polysilicon sheet resistance, and N-sheet contact chain resistance, rather than with others, like NMOS breakdown voltage, which correlated poorly. As a new result, positive correlation between good device yield and a strong near-surface strain gradient is found by synchrotron X-ray topography. Unexpectedly, computed from the etch-pit micrographs, the yield correlates very poorly to the defect-free zone depth of the wafer surface. The results suggests that strain has more impact on the operation of the electronic device than precipitates solely would have.